LTPS-LCD structure and method for manufacturing the same

ABSTRACT

An LTPS-LCD structure and a method for manufacturing the structure are provided. The structure comprises a substrate where a plurality of pixels are formed thereon. Each of these pixels comprises a control area, a capacitance area, and a display area. The structure is initially formed with a transparent electrode on the substrate, followed by a control device, a capacitance storage device. The display unit is then formed on the control area, the capacitance area, and the display area, respectively. As a result, the capacitance of the structure can be enhanced and the manufacturing processes of masks can be reduced.

This application claims the benefits of Taiwan Patent Application No.095126657, filed Jul. 21, 2006, the contents of which are hereinincorporated by reference in its entirety.

CROSS-REFERENCES TO RELATED APPLICATIONS

Not applicable.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an LCD structure and a method formanufacturing the structure. In particular, the invention relates to anLTPS-TFT LCD structure and a method for manufacturing the structure toreduce photolithography processes with masks and simultaneously enhancepixel capacitance.

2. Descriptions of the Related Art

Liquid crystal displays (LCDs) are mainstream products on the displaymarket. Not only do LCDs save power and emit low radiation, they arealso lightweight and portable. Technologies of thin-film-transistor LCD(TFT-LCD) can be classified into two groups: amorphous silicon (α-Si)and poly-silicon (Poly-Si). The technology and techniques of α-Si arefully developed and frequently used in TFT-LCDs on the display market.

However, low temperature poly silicon (LTPS) is a recent and noveltechnology for manufacturing Poly-Si LCDs. In comparison withconventional α-Si LCDs, carrier mobility on the LTPS TFT is at least twohundred times higher than that on the α-Si TFT due to itscharacteristics. The displays which utilize LTPS technology also havehigher performance, with shorter response time and greater brightness,resolution, and color saturation. Therefore, LTPS-LCD can present imageswith higher display quality. Moreover, the physical structure andelements in the LTPS-LCDs can be minimized, so the TFT module area is atleast 50% smaller. Thus, LTPS-LCDs can be thinner and lighter to reducepower exhausting. The size advantage of the TFT modules also reducesmanufacturing costs of the LTPS-LCDs as well. Because of the manyadvantages present by LTPS technology, LTPS-LCDs attract lots ofattentions on the LCD market.

In the conventional LTPS photolithography manufacturing processes, sixmasks are usually involved. These processes for manufacturing an LPTSdisplay structure 10 are outlined in FIGS. 1A˜1F. For illustration, aTFT 11 and a capacitance storage device 13 are merely shown in thefigures. Firstly, FIG. 1A shows the photolithography process with thefirst mask. Poly-silicon islands 110, 130 are formed onto a substrate100 to function as fundamental materials for the TFT 11 and thecapacitance storage device 13.

Referring to FIG. 1B, the photolithography process with the second maskis illustrated. A lower insulator layer 12 is formed to cover theaforesaid poly-silicon islands 110, 130. Then, first conductive layers113, 133 are respectively formed on the lower insulator layer 12.Subsequently, as shown the arrows in FIG. 1B, the poly-silicon islands110 are doped with P+ and P− ions to turn into a source/drain structure.

After that, as shown in FIG. 1C, an upper insulator layer 14 covers theaforesaid first conductive layer 113, 133 and the lower insulator layer12. Two contact holes 141 are then formed by the photolithographyprocess with the third mask. The contact holes 141 are utilized toexpose the source/drain structure for following electrical conduction.

The photolithography process with the fourth mask is shown in FIG. 1D.Second conductive layers 115, 135 are formed, in which the secondconductive layer 115 connects the source/drain structure within thecontact hole 141. The other second conductive layer 135 iscorrespondingly formed above the first conductive layer 133. As aresult, a MIM (metal-insulator-metal) capacitance is formed between thefirst conductive layer 133 and the second conductive layer 135.

Referring to FIG. 1E, a passivation layer 16 is formed to cover theabove mentioned elements. Then, the photolithography process with thefifth mask can be proceeded to form a contact hole 161 for partiallyexposing the second conductive layer 115 which is connecting with thedrain structure.

Finally, a transparent electrode 17 is formed by the photolithographyprocess with the sixth mask. The transparent electrode 17 electricallyconnects with the second conductive layer 115 at the contact hole 161and further connects to a display area (not shown) of the pixel forproviding the required electric fields.

However, the conventional LTPS display structure 10 still hasdisadvantageous limitations. As shown in FIG. 1B, the poly-siliconisland 130 that is sheltered from the first conductive layer 133 cannotbe doped during the doping process. Consequently, the final productwould not have any effective capacitance between the first conductivelayer 133 and the poly-silicon island 130. As a result, the capacitanceprovided from the display structure 10 is substantially reduced.Furthermore, because of the complicated manufacturing processes of theconventional structure, more photolithography processes with masks arerequired, raising the cost of manufacturing.

Given the above, an LTPS-LCD structure which can be made from simplifiedphotolithography processes and promote capacitances needs to bedeveloped in this field.

SUMMARY OF THE INVENTION

The primary objective of this invention is to provide an LTPS-LCDstructure. By previously disposing a transparent electrode on the bottomof the display structure, an effective capacitance can be generatedwithin the un-doped poly-silicon area. Thus, the capacitance of thefinal product can be promoted to benefit effective operation of thedisplay structure.

Another objective of this invention is to provide a method formanufacturing the LTPS-LCD structure. By disposing the transparentelectrode during the previous photolithography process, the processesfor manufacturing the entire TFT and capacitance storage device can besimplified to effectively economize costs and shorten manufacturingperiods.

To achieve the aforementioned objectives, an LTPS-LCD structure isprovided in the present invention. The structure comprises a substrate,a transparent electrode, a lower insulator layer, a control device, afirst conductive layer, an upper insulator layer, and a secondconductive layer. The substrate is formed with a plurality of pixelareas each including a control area, a capacitance area, and a displayarea. The transparent electrode is formed on the substrate thatcorresponds to the display area, the control area, and the capacitancearea. The lower insulator layer is formed on the transparent electrodethat corresponds to the control area. The control device is formed onthe lower insulator layer that corresponds to the control area. Thefirst conductive layer is partially formed on the control device and thetransparent electrode that corresponds to the control area and thecapacitance area respectively. The upper insulator layer at leastpartially covers the control device and the first conductive layer. Thesecond conductive layer at least partially covers the upper insulatorlayer for forming a capacitance storage device with the first conductivelayer on the capacitance area, whereby it electrically connects thecontrol device to the transparent electrode disposed on the displayarea.

A method for manufacturing the aforementioned LTPS-LCD structure is alsoprovided in the present invention. The method comprises the followingsteps: forming the transparent electrode on the display area, thecontrol area, and the capacitance area of the substrate; forming asilicon-oxide insulator layer that corresponds to the control area;locally forming a first conductive layer on the silicon-oxide insulatorlayer and the transparent electrode that corresponds to the control areaand the capacitance area, and forming the control device on the controlarea; forming an upper insulator layer which at least partially coveringthe control device and the first conductive layer; and forming a secondconductive layer which at least partially covering the upper insulatorlayer to form a capacitance storage device with the first conductivelayer.

The detailed technology and preferred embodiments implemented for thesubject invention are described in the following paragraphs accompanyingthe appended figures for people skilled in this field to well appreciatethe features of the claimed invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1F are schematic views illustrating the manufacturingprocesses of the conventional LTPS display structure;

FIGS. 2A and 2B are schematic views illustrating the photolithographyprocess with the first mask of a preferred embodiment of the presentinvention;

FIG. 3 is a schematic view illustrating the photolithography processwith the second mask of the preferred embodiment of the presentinvention;

FIG. 4 is a schematic view illustrating the photolithography processwith the third mask of the preferred embodiment of the presentinvention;

FIG. 5 is a schematic view illustrating the photolithography processwith the fourth mask of the preferred embodiment of the presentinvention; and

FIG. 6 is a schematic view illustrating the photolithography processwith the fifth mask of the preferred embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A preferred embodiment of the LTPS-LCD structure of the presentinvention is shown in FIG. 6, and preferred processes for manufacturingthe structure are shown from FIG. 2A through FIG. 6.

The LTPS-LCD structure 20 of the present invention comprises a controldevice 51, a capacitance storage device 53, and a pixel unit 55.Referring to FIGS. 2A and 2B, the structure 20 comprises a substrate 200which is formed with a plurality of pixel areas. To specificallydisclose the present invention, only a pixel area 30 is representativelyshown in the figures. Each pixel area 30 includes a control area 31, acapacitance area 33, and a display area 35.

As shown in FIG. 2B, a transparent electrode 21 is previously formed onthe control area 31, the capacitance area 33, and the display area 35 ofthe substrate 200. Preferably, the transparent electrode 21 is made ofIndium Tin Oxide (ITO). Then, a silicon-oxide insulator layer 22 (ornamely a lower insulator layer) is formed on the transparent electrode21 that corresponds to the control area 31. A poly-silicon layer 23 isthen formed on the silicon-oxide insulator layer 22, wherein thesilicon-oxide insulator layer 22 and the poly-silicon layer 23 areformed with a predetermined pattern.

In FIG. 2A, the above-mentioned manufacturing process is illustratedmore specifically. The transparent electrode 21, the silicon-oxideinsulator layer 22, and the poly-silicon layer 23 are successivelyformed on the substrate 200, and a photolithography (etching) process issubsequently performed. That is to say, the silicon-oxide insulatorlayer 22 is also formed on the transparent electrode 21 that correspondsto the capacitance area 33 and the display area 35. Similarly, thepoly-silicon layer 23 is also formed on the silicon-oxide insulatorlayer 22 that corresponds to the control area 31, the capacitance area33, and the display area 35.

Subsequently, photo-resist layers 41, 43, 45 are respectively disposedonto the poly-silicon layer 23 corresponding to the control area 31, thecapacitance area 33, and the display area 35. Preferably, thephoto-resist layers 41, 43, 45 are made from a half-tone mask. It isfurther noted that the photo-resist layers 41, 43, 45 have differentpredetermined thicknesses due to the half-tone mask process. Forexample, a photolithography process with the first mask of the presentinvention is provided by etching the photo-resist layer 41 which has agreater thickness. Because the photo-resist layers 43 and 45 arethinner, the poly-silicon layer 23 and the silicon-oxide insulator layer22 on the display area 35 can be removed with etching, leaving only thetransparent electrode 21. Similarly, the poly-silicon layer 23 on thecapacitance area 33 can be removed as well. Preferably, due to thespecific thickness of the photo-resist layer 43, the silicon-oxideinsulator layer 22 on the capacitance area 22 can be removed completelyafter etching. As a result of these processes, the capacitance storagedevice 53 of the final product can have a higher capacitance.

With reference to FIG. 3, first conductive layers 25, 25′ are partiallyformed on the transparent electrode 21 that corresponds to the controlarea 31 and the capacitance area 33. In this case, the first conductivelayer 25 is formed as a gate structure on the control area 31. Morespecifically, a mid-insulator layer 24 is previously formed thatcorresponds to the control area 31, the capacitance area 33, and thedisplay area 35. Then, the photolithography process with the second maskof the present invention is performed. The first conductive layers 25,25′ are respectively formed that corresponds to the control area 31 andthe capacitance area 33. Finally, the control device 51 is doped into asource electrode 231 and a drain electrode 232 on the control area 31.Preferably, the control device 51 is partially performed with a lightlydoped drain (LDD) process to form an LDD structure for higherconductivity.

Following the aforesaid processes, an upper insulator layer 26 is formedas shown in FIG. 4. The upper insulator layer 26 at least partiallycovers the control device 51 and the first conductive layers 25, 25′.Furthermore, the upper insulator layer 26 is formed to cover theaforesaid elements. Then, two contact holes 261, 262 are formed by aphotolithography process with the third mask. The source electrode 231and the drain electrode 232 can be exposed from the upper insulatorlayer 26 and the mid-insulator layer 24 for electrical connection.

The photolithography process with the fourth mask of the presentinvention is shown in FIG. 5. According to the above-mentionedstructure, second conductive layers 271, 272 are formed to at leastpartially cover the upper insulator layer 26. Accordingly, thecapacitance storage device 53 is formed between the second conductivelayer 272 and the first conductive layer 25′, and the control device 51is electrically connected to the transparent electrode 21 on the displayarea 35 to form the required electric fields. More specifically, thesecond conductive layers 271, 272 connect onto the source electrode 231and the drain electrode 232 of the control device 51 through the contactholes 261, 262 in the upper insulator layer 26 and the mid-insulatorlayer 24.

Finally, as shown in FIG. 6, the photolithography process with the fifthmask of the present invention forms a passivation layer 28 to cover theLTPS-LCD structure 20 on the second conductive layer 271, 272.

In accordance with the aforesaid manufacturing processes, the LTPS-LCDstructure 20 of the present invention is obtained. On the control area31, the structure 20 successively comprises the substrate 200, thetransparent electrode 21, the lower insulator layer 22, the controldevice 51, the mid-insulator layer 24, the first conductive layer 25,the upper insulator layer 26, the second conductive layer 271, and thepassivation layer 28. On the capacitance area 33, preferably, thestructure 20 successively comprises the substrate 200, the transparentelectrode 21, the mid-insulator layer 24, the first conductive layer25′, the upper insulator layer 26, the second conductive layer 272, andthe passivation layer 28. However, on the display area, only thesubstrate 200 and the transparent electrode 21 remain.

Specifically, the lower insulator layer 22 is formed on the transparentelectrode 21 to correspond to the control area 31 and the capacitancearea 33. Alternatively, the lower insulator layer 22 can simply beformed on the control area 31 to generate a higher capacitance withoutthe lower insulator layer 22 on the capacitance area 33. Correspondingto the control area 31, the control device 51 is formed on the lowerinsulator layer 22. Preferably, the mid-insulator layer 24 is disposedunder the first conductive layers 271, 272. That is to say, the firstconductive layer 271, 272 are partially formed on the control device 51and the transparent electrode 21 that corresponds to the control area 31and the capacitance area 33, respectively. The upper insulator layer 26at least partially covers the control device 51 and the first conductivelayers 25, 25′. The second conductive layers 271, 272 at least partiallycover the upper insulator layer 26, to form the capacitance storagedevice 53 with the first conductive layer 25′ and electrically connectthe control device 51 to the transparent electrode 21 on the displayarea 55.

Preferably, the control device 51 is a thin-film-transistor (TFT) andthe lower insulator layer 22 can be the silicon-oxide insulator layer22. The passivation layer 28 completely covers the second conductivelayer 271, 272.

According to the above-mentioned LTPS-LCD structure 20 of the presentinvention, the transparent electrode 21 is previously formed on thesubstrate 200. This structure can not only enhance the efficiency of thecapacitance storage device, but can also diminish the number of stepswithin the photolithography processes or etching processes with masksfrom six to five. This can substantially reduce costs and shortenmanufacturing processes.

The above disclosure is related to the detailed technical contents andinventive features thereof. People skilled in this field may proceedwith a variety of modifications and replacements based on thedisclosures and suggestions of the invention as described withoutdeparting from the characteristics thereof. Although such modificationsand replacements are not fully disclosed in the above descriptions, theyhave substantially been covered in the following claims as appended.

1. A method for manufacturing an LTPS-LCD structure, the structurecomprising a substrate which is formed with a plurality of pixel areaseach including a control area, a capacitance area, and a display area;the method comprising the steps of: (a) forming a transparent electrodeon the display area, the control area, and the capacitance area of thesubstrate, and forming a silicon-oxide insulator layer on thetransparent electrode to correspond to the control area; (b) locallyforming a first conductive layer on the silicon-oxide insulator layerand the transparent electrode to correspond to the control area and thecapacitance area, respectively, and forming a control device on thecontrol area; (c) forming an upper insulator layer which at leastpartially covering the control device and the first conductive layer;and then (d) forming a second conductive layer which at least partiallycovering the upper insulator layer to form a capacitance storage devicewith the first conductive layer, whereby electrically connects thecontrol device to the transparent electrode disposed on the displayarea.
 2. The method as claimed in claim 1, in which after the step (d)further comprises the step of: (e) forming a passivation layer coveringthe second conductive layer.
 3. The method as claimed in claim 1,wherein the step (a) further comprises the steps of: (a-1) forming asilicon-oxide insulator layer on the transparent electrode to correspondto the capacitance area and the display area; and then (a-2) forming apoly-silicon layer on the silicon-oxide insulator layer to correspond tothe control area, the capacitance area, and the display area.
 4. Themethod as claimed in claim 3, wherein the silicon-oxide insulator layerand the poly-silicon layer forms a predetermined pattern which is formedby the step of: (a-3) etching a photo-resist layer which is disposed onthe poly-silicon layer to correspond to the control area, thecapacitance area, and the display area.
 5. The method as claimed inclaim 4, the step (a-3) employs a half-tone mask process.
 6. The methodas claimed in claim 4, wherein the step (b) further comprises the stepsof: (b-1) forming a mid-insulator layer to correspond to the controlarea, the capacitance area, and the display area; (b-2) forming thefirst conductive layer to correspond to the control area and thecapacitance area; (b-3) doping the control device to form a sourceelectrode and a drain electrode; and (b-4) doping the control device toform a low doped structure thereof.
 7. The method as claimed in claim 6,wherein the step (c) further comprises the step of: (c-1) exposing thesource electrode and the drain electrode from the upper insulator layerand the mid-insulator layer.
 8. The method as claimed in claim 7,wherein in the step (d), the second conductive layer connects thecontrol device onto the source electrode and the drain electrode throughthe upper insulator layer and the mid-insulator layer.